Research

In this work, we employ 3D technology computer-aided design (TCAD) mixed-mode simulations to investigate single-event effects (SEE) in FeRAM across three distinct access-transistor geometries, prioritizing heavy-ion impingement on the access transistor. We evaluate write, hold, and read operations to elucidate the device response under varying bias configurations. The simulations are coupled with a regenerative voltage-latch sense amplifier implemented using 32 nm PTM low-power (LP) transistor models to realize the logical manifestation of the single-event effects. Under heavy-ion irradiation, the internal polarization dynamics exhibit a state-dependent response. For the Data 1 state, heavy-ion–induced charge deposition produces an electric field that degrades polarization, whereas in the Data 0 state, the induced field is constructive. This asymmetry arises from state-dependent electrostatics at the storage node. The degradation in the Data 1 state is further amplified by residual charge due to the parasitic bipolar effect present in bulk transistors. Additionally, the sense amplifier topology, whether single-ended or double-ended/differential, strongly influences the available sensing margin and thus the read robustness under radiation events.

Residual charge at the storage node sets the vulnerability. After a BL-Last write disable it leaves the storage node-to-body junction reverse biased, which provides the conditions for parasitic bipolar amplification of the strike; BL-First depletes it before sensing. In bulk planar devices the amplified transient pulls the node negative and counter-writes Data 1, with 52–86% polarization loss at high LET, whereas SOI and VFET geometries truncate the bipolar path. Sensing failure then depends on the timing of the strike relative to bitline signal development, and a 2T2C bit cell is projected to give a 1.77× hardening gain for C_BL = 10 fF and C_FE = 3 fF.

Threshold voltage variability is a key concern in ferroelectric field effect transistor (FeFET) technology. In this work, a study spanning experiments, modeling, and SPICE simulations is conducted to evaluate the impact of localized FE/ dielectric (DE) distributions on the threshold voltage (V_TH) of FeFET. The device characterization is performed on the 28-nm FeFET foundry platform. The experimental study on device-to-device (D2D) and cycle-to-cycle (C2C) variations reveals that the FeFET can be an asymmetric device, with the V_TH showing dependence on the direction of current flow, as well as the magnitude of applied drain voltage (V_DS) to the device. The TCAD modeling study reveals that the cause of asymmetry is the spatial localization of DE phases that may occur due to the random nature of the distribution. SPICE simulation for two-FeFET-based ternary content-addressable memory (TCAM) reveals that as few as two devices exhibiting the localization-induced threshold voltage shift can lead to a 64-bit search failure. Various strategies are investigated to minimize the impact of such localized phase distribution-induced threshold voltage shift (LPTS) effect. Notably, the capacitive readout of FeFET and the insertion of a floating metal electrode in the gate-stack improve the robustness.

Localized FE/DE phases produce a localized barrier at the channel surface, so V_TH depends on the direction of current flow. Capacitive (nvCAP) readout shorts the source and drain and is robust to this, as is an MFMIS stack, where a floating metal electrode screens the phase variation; however, nvCAP still exhibits read-after-write delay and capacitive sneak current in arrays, and MFMIS complicates scaling, retention, and write voltage. Reliability testing of FeFETs should use electrical conditions consistent with the end application.

NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (V_th) degradation under ionizing radiation, causing reliability challenges for space and defense applications. Here we show that ferroelectric field-effect transistors (FeFETs) with laminated gate stacks offer a promising route to achieving radiation resilience in vertical NAND technology. We demonstrate that large-memory-window, vertical NAND-compatible laminated poly-silicon-channel FeFETs with an 8 nm Hf_0.5Zr_0.5O₂/3 nm Al₂O₃/8 nm Hf_0.5Zr_0.5O₂ stack retain a full memory window and robust switching up to 10 Mrad(air) of the total ionizing dose (TID). Programmed and erased states show negligible TID-induced drift after 1 Mrad(air), while only the erased state degrades by ∼2 V at 10 Mrad(air). Technology computer-aided design (TCAD) modeling attributes these asymmetric shifts to state-dependent traps. Compared to charge-trap NAND, laminated FeFETs exhibit ∼30-fold lower V_th degradation per unit dose, positioning them as superior radiation-resilient storage candidates.

The TID-induced V_th shift depends on where the traps form. In the erased state, hole trapping near the channel-side interlayer shifts V_th, while traps in the Al₂O₃ or at the FE/Al₂O₃ interface have little effect. The shifts can be corrected by adjusting the read-reference and erase-verify voltages with absorbed dose. CMOS charge pumps in NAND typically fail beyond ~100 krad, so a hardened charge pump is still needed for a fully hardened FeFET SSD.

Rapid advancements in semiconductor technologies have enabled circuit operation at gigahertz (GHz) frequencies. However, conventional radiation hardening by design (RHBD) methods may encounter challenges in the GHz frequency domain, leading to increased single-event upset (SEU) rates. In this study, the SEU susceptibility of flip-flop (FF) designs in a 5-nm bulk FinFET technology node, both with and without hardening techniques, operating at frequencies up to 0.7 GHz are assessed. Comprehensive experiments involving heavy-ion and alpha particles were conducted across a wide range of supply voltages and frequencies to investigate the SEU cross sections. Results demonstrate the relationship between SEU cross section, operating frequency, and particle linear energy transfer (LET) values for FF designs employing temporal and spatial hardening techniques. Notably, all hardened designs examined in this work exhibit significantly higher SEU cross sections when operating at 0.7 GHz compared to 2.5 MHz, approaching or surpassing the SEU cross section of an unhardened conventional D-FF. These findings underscore the significance of considering high-frequency and dynamic operational data, as relying solely on static or low-frequency information can lead to a substantial underestimation of SEU cross sections, thereby elevating failure rates in deployed electronic systems.

The probability that a transient is latched rises with frequency as the clock period approaches the SET pulsewidth. At 0.7 GHz, the DICE, guard-gate, and Schmitt-trigger flip-flops show similar cross sections, which removes the order-of-magnitude advantage DICE has in static testing. Soft-error predictions for scaled nodes should therefore be based on high-frequency data.

This work addresses a key bottleneck in radiation hardened computing: achieving high-density embedded memory in monolithically stacked (M3D) systems without relying on area inefficient SRAM or radiation-sensitive scaled Si access devices. We evaluate back-end-of-the-line (BEOL) compatible Ga-doped indium oxide (IGO) MOSFETs as access transistors for vertically integrated 1T-1C embedded DRAM (eDRAM) under both ionizing and displacement-damage radiation. Devices are subjected to ⁶⁰Co gamma total-ionizing-dose (γ-TID) up to 10 MRad(air) and neutron fluence up to 10¹⁵ n/cm². IGO MOSFETs exhibit exceptional γ-TID tolerance: transfer characteristics, threshold voltage (V_Th), and effective mobility remain statistically invariant up to 10 MRad, and sub-gap density-of-states (DOS) extraction from multi-frequency CV confirms negligible ionization-induced defect generation. In contrast, neutron irradiation produces pronounced displacement damage, manifested as positive V_th shifts, mobility degradation, and increased mid-gap and band-tail defect densities. Bias-temperature-instability (BTI) measurements show radiation accelerated parameter drift; enhanced PBTI is consistent with activation of deep traps in the HfO₂ gate dielectric, while increased NBTI is consistent with radiation-assisted hydrogen diffusion. Calibrated TCAD reproduces these trends, linking γ TID primarily to modest interface-state increases and neutrons to broader/deeper defect spectra. System-level analysis indicates IGO-based 1T-1C eDRAM achieves ∼500× higher retention than silicon baselines and only a 2% retention penalty at 10 MRad (vs ∼42% for Si FinFETs), positioning BEOL IGO as a scalable access-device platform for dense, radiation-hardened monolithic eDRAM.

The γ-TID response is captured by a modest increase in interface acceptor traps at the HfO₂/IGO interface, with no change to the bulk channel DOS. Neutron irradiation requires broader and higher acceptor-like distributions in the IGO DOS, in addition to more interface trapping, to reproduce the V_TH shift and mobility loss. BTI is accelerated after both exposures, with larger |ΔV_TH| after neutrons; margins are governed primarily by displacement damage and BTI acceleration.

Phase variations in the ferroelectric thin films are the primary cause of the threshold voltage (V_TH) variation in the Ferroelectric Field Effect Transistor (FeFET). In this work, the impact of "localized" ferroelectric/dielectric (FE/DE) phase variation on FeFET is evaluated. A new phenomenon, namely, Localized Phase Distribution Induced Threshold Voltage Shift (LPTS), is experimentally characterized. Here, a scaled FeFET exhibits an asymmetric current readout that leads to a threshold voltage (V_TH) shift that is dependent on the direction of current flow (when source and drain are flipped). The device characterization with device-to-device and cycle-to-cycle variations is performed on 28 nm bulk Si FeFET technology platform. The supporting TCAD simulations point towards the presence of an uneven number of FE/DE phases near Source-Channel vs Drain-Channel boundary to be the main cause of asymmetric current readout. Further, the simulation indicates that the novel non-destructive "capacitive" readout of a scaled FeFET to be more robust towards phase variation compared to the traditional current readout as the LPTS effect is amortized.

TCAD with an 80%/20% FE/DE distribution and all DE phases at the drain–channel boundary gives ~500 mV of ΔV_TH for the PGM state; a random phase map gives ~250 mV. The asymmetry develops after a program operation and is reduced almost immediately by an erase. nvCAP readout is robust against LPTS, but read-after-write delay persists.